I am an Assistant Professor at Electrical-Electronics Engineering Department at Istanbul Commerce University. My current research interests are:

  • Security in the Internet of Things
  • Fully Homomorphic Encryption Schemes
  • Physical Unclonable Functions
  • Lightweight and fault-tolerant cryptographic applications
  • Efficient implementations of cryptographic algorithms

PUBLICATIONS
Journal Papers

  1. Erdinç Öztürk, Yarkın Doröz, Erkay Savaş, Berk Sunar. A Custom Accelerator for Homomorphic Encryption Applications. IEEE Transactions on Computers, 2016.
  2. Yarkın Doröz, Erdinç Öztürk and Berk Sunar, Accelerating Fully Homomorphic Encryption in Hardware. IEEE TRANSACTIONS ON COMPUTERS, 64(6), 1509-1521, 2015.
  3. Erdinç Öztürk, Yarkın Doröz, Berk Sunar and Erkay Savaş, Accelerating Somewhat Homomorphic Evaluation using FPGAs. Cryptology ePrint Archive: Report 2015/294.
  4. Yarkın Doröz, Erdinç Öztürk and Berk Sunar, A million-bit multiplier architecture for fully homomorphic encryption, MICROPROCESSORS AND MICROSYSTEMS, 38(8), 766-775, 2014
  5. Erdinç Öztürk, Erkay Savas, Berk Sunar. A Versatile Montgomery Multiplier Architecture with Characteristic Three Support. Computers and Electrical Engineering Journal, Volume 35, Issue 1, Pages 71-85, Elsevier Science Publishers B. V. Amsterdam, The Netherlands, January 2009.
  6. Ghaith Hammouri, Erdinç Öztürk, Berk Sunar. A Tamper-Proof and Lightweight Authentication Scheme. Pervasive and Mobile Computing Journal, Volume 4, Issue 6, Pages 807-818, Elsevier Science Publishers B. V. Amsterdam, The Netherlands, 2008.

Editor

  1. Thomas Eisenbarth, Erdinç Öztürk. Lightweight Cryptography for Security and Privacy – Third International Workshop, LightSec 2014, Istanbul, Turkey, September 1-2, 2014, Revised Selected Papers. Lecture Notes in Computer Science 8898, Springer 2015, ISBN 978-3-319-16362-8

Conference Papers

  1. Yarkın Doröz, Erdinç Öztürk, Erkay Savaş and Berk Sunar, Accelerating LTV Based Homomorphic Encryption in Reconfigurable Hardware. Workshop on Cryptographic Hardware and Embedded Systems 2015 (CHES 2015), Saint Malo, France.
  2. Yarkın Doröz, Erdinç Öztürk and Berk Sunar, Evaluating the Hardware Performance of a Million-bit Multiplier. Euromicro Conference on Digital System Design (DSD 2013), Santander, Spain.
  3. Vinodh Gopal, James Guilford, Erdinç Öztürk, Wajdi Feghali, Gil Wolrich, Martin Dixon. Fast and Constant-Time Implementation of Modular Exponentiation. 28th International Symposium on Reliable Distributed Systems, September 27-30, 2009. Niagara Falls, New York, USA.
  4. Ghaith Hammouri, Erdinç Öztürk, Berk Birand, Berk Sunar. Unclonable Lightweight Authentication Scheme. In Proceedings of Information and Communications Security, 10th International Conference (ICICS 2008), Liqun Chen, Mark Dermot Ryan, Guilin Wang (Eds.) Birmingham, UK, October 20-22, 2008, Lecture Notes in Computer Science 5308 Springer Verlag, Pages 33-48, 2008.
  5. Erdinç Öztürk, Ghaith Hammouri, Berk Sunar. Physical Unclonable Function with Tristate Buers. In Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Seattle, Washington, USA, pp. 3194-3197, IEEE, Washington, DC, USA (2008).
  6. Erdinç Öztürk, Berk Sunar, Ghaith Hammouri. Towards Robust Low Cost Authentication for Pervasive Devices. The Sixth Annual IEEE International Conference on Pervasive Computing and Communications, March 17-21, 2008, Hong Kong.
  7. Erdinç Öztürk, Gunnar Gaubatz, Berk Sunar. Tate Pairing With Strong Fault Resiliency. In Luca Breveglieri, Shay Gueron, Israel Koren, David Naccache, and Jean-Pierre Seifert, Editors, FDTC, Pages 103-111. IEEE Computer Society, 2007.
  8. Gunnar Gaubatz, Jens Peter Kaps, Erdinç Öztürk, Berk Sunar. State of the Art in Ultra-Low Power Public Key Cryptography for Wireless Sensor Networks. In Third IEEE International Conference on Pervasive Computing and Communications Workshops, 2005, Pages 146-150.
  9. Erdinç Öztürk, Berk Sunar, Erkay Savas. Low-Power Elliptic Curve Cryptography Using Scaled Modular Arithmetic. In Marc Joye and Jean-Jacques Quisquater, Editors, CHES, Volume 3156 of Lecture Notes in Computer Science, Pages 92-106. Springer, 2004.

Intel White Papers

  1. Erdinç Öztürk, Jim Guilford, Vinodh Gopal, Wajdi Feghali. New Instructions Supporting Large Integer Arithmetic on Intel Architecture Processors. August 2012, Intel White Paper.
  2. Vinodh Gopal, Jim Guilford, Chengda Yang, Wajdi Feghali, Erdinç Öztürk, Gil Wolrich, Kirk Yap, Martin Dixon. High Performance DEFLATE Compression on Intel Architecture Processors. November 2011, Intel White Paper.
  3. Vinodh Gopal, Jim Guilford, Erdinç Öztürk, Sean Gulley, Wajdi Feghali. Improving OpenSSL Performance. October 2011, Intel White Paper.
  4. Vinodh Gopal, Jim Guilford, Erdinç Öztürk, Gil Wolrich, Wajdi Feghali, Martin Dixon, Deniz Karakoyunlu. Fast CRC Computation for iSCSI Polynomial Using CRC32 Instruction. April 2011, Intel White Paper.
  5. Vinodh Gopal, Jim Guilford, Wajdi Feghali, Erdinç Öztürk, Gil Wolrich, Kirk Yap, Sean Gulley, Martin Dixon. Cryptographic Performance on the 2nd Generation Intel Core Processor Family. January 2011, Intel White Paper.
  6. Kahraman Akdemir, Martin Dixon, Wajdi Feghali, Patrick Fay, Vinodh Gopal, Jim Guilford, Erdinç Öztürk, Gil Wolrich, Ronen Zohar. Breakthrough AES Performance with Intel AES New Instructions. 2010, Intel White Paper.
  7. Vinodh Gopal, Jim Guilford, Chengda Yang, Wajdi Feghali, Erdinç Öztürk, Gil Wolrich, Kirk Yap, Martin Dixon. High Performance DEFLATE Decompression on Intel Architecture Processors. November 2010, Intel White Paper.
  8. Vinodh Gopal, Erdinç Öztürk, Wajdi Feghali, Jim Guilford, Gil Wolrich, Martin Dixon. Optimized Galois-Counter-Mode Implementation on Intel Architecture Processors. August 2010, Intel White Paper.
  9. Vinodh Gopal, Erdinç Öztürk, Wajdi Feghali, Jim Guilford, Gil Wolrich, Kirk Yap, Martin Dixon. High Performance Storage Encryption on Intel Architecture Processors. August 2010, Intel White Paper.
  10. Vinodh Gopal, Jim Guilford, Wajdi Feghali, Erdinç Öztürk, Gil Wolrich, Martin Dixon. Processing Multiple Buffers in Parallel to Increase Performance on Intel Architecture Processors. July 2010, Intel White Paper.
  11. Vinodh Gopal, Wajdi Feghali, Jim Guilford, Erdinç Öztürk, Gil Wolrich, Martin Dixon, Max Locktyukhin, Maxim Perminov. Fast Cryptographic Computation on Intel Architecture Processors via Function Stitching. April 2010, Intel White Paper.
  12. Vinodh Gopal, Erdinç Öztürk, Jim Guilford, Gil Wolrich, Wajdi Feghali, Martin Dixon. Fast CRC Computation for Generic Polynomials Using PCLMULQDQ Instruction. December 2009, Intel White Paper.

Patents (Owned by Intel)

  1. Instructions Processors, Methods, And Systems to Process Blake Secure Hashing Algorithm (US Patent 9,100,184)
  2. Efficient multiplication, exponentiation and modular reduction implementations (US Patent 9,092,645)
  3. Method and Apparatus for Efficient Programmable Cyclic Redundancy Check (CRC) (US Patent 9,052,985)
  4. Method and Apparatus to Process SHA-1 Secure Hashing Algorithm (US Patent 8,954,754)
  5. Enhancing Performance by Instruction Interleaving and/or Concurrent Processing of Multiple Buffers (US Patent 8,930,681)
  6. Instructions to Perform Groestl Hashing (US Patent 8,929,539)
  7. Unified system architecture for elliptic-curve cryptography (US Patent 8,781,110)
  8. Add instructions to add three source operands (US Patents 8,738,893  8,549,264)
  9. Method and apparatus for expansion key generation for block ciphers (US Patent 8,520,845)
  10. Rotate instructions that complete execution without reading carry flag (US Patent 8,504,807)
  11. Method and apparatus for performing efficient side-channel attack resistant reduction using montgomery or barrett reduction (US Patent 8,392,494)
  12. Method and apparatus for advanced encryption standard (AES) block cipher (US Patent 8,391,475)
  13. Normal-basis to canonical-basis transformation for binary galois-fields GF(2^m) (US Patent 8,380,777)
  14. Polynomial-basis to normal-basis transformation for binary Galois-Fields GF(2^m) (US Patent 8,380,767)
  15. Efficient Advanced Encryption Standard (AES) Datapath Using Hybrid Rijndael S-Box (US Patent 8,346,839)
  16. Residue Generation (US Patent 8,312,363)
  17. Unified Integer/Galois Field (2m) Multiplier Architecture For Elliptic-Curve Crytpography (US Patent 8,271,570)
  18. Determining A Message Residue (US Patent 8,042,025)
  19. Modulus Scaling For Elliptic-Curve Cryptography (US Patent 8,005,210)
  20. Efficient Elliptic-Curve Cryptography Based on Primality of the Order of the ECC-Group (US Patent 7,986,779)
  21. Scale-Invariant Barrett Reduction For Elliptic-Curve Cyrptography (US Patent 7,978,846)
  22. Factoring Based Modular Exponentiation (US Patent 7,961,877)
  23. Method for Simultaneous Modular Exponentiations (US Patent 7,925,011)
  24. Method And Apparatus for Testing Mathematical Algorithms (US Patent 7,730,356)
  25. Rotate Instructions That Complete Execution Either Without Writing Or Reading Flags (US Patent Application, March 26, 2015)
  26. Method And Apparatus For Performing A Shift And Exclusive Or Operation In A Single Instruction (US Patent Application, March 26, 2015)
  27. SIMD Integer Multiply-Accumulate Instruction for Multi-Precision Arithmetic (US Patent Application, August 21, 2014)
  28. Instructions To Perform JH Cryptographic Hashing in a 256 Bit Data Path (US Patent Application, July 24, 2014)
  29. Three Input Operand Vector Add Instruction That Does Not Raise Arithmetic Flags For Cryptographic Applications (US Patent Application, July 10, 2014)
  30. Method and Apparatus To Process SHA-2 Secure Hashing Algorithm (US Patent Application, July 10, 2014)
  31. Instruction for Accelerating Snow 3G Wireless Security Algorithm (US Patent Application, July 3, 2014)
  32. Methods, Systems And Apparatus To Reduce Processor Demands During Encryption (US Patent Application, June 26, 2014)
  33. Apparatus And Method For Vector Instructions For Large Integer Arithmetic (US Patent Application, June 12, 2014)
  34. Bitstream Processing Using Coalesced Buffers And Delayed Matching And Enhanced Memory Writes (US Patent Application, June 5, 2014)
  35. Apparatus And Method Of Execution Unit For Calculating Multiple Rounds Of A Skein Hashing Algorithm (US Patent Application, May 1, 2014)
  36. Method And Apparatus To Process 4-Operand SIMD Integer Multiply-Accumulate Instruction (US Patent Application, March 20, 2014)
  37. Instructions To Perform JH Cryptographic Hashing (US Patent Application, February 20, 2014)
  38. Method for Fast Large-Integer Arithmetic on IA Processors (US Patent Application, January 16, 2014)
  39. Addition Instructions with Independent Carry Chains (US Patent Application, January 9, 2014)
  40. Matrix Multiply Accumulate Instruction (US Patent Application, January 2, 2014)
  41. Techniques to Accelerate Lossless Compression (US Patent Application, January 2, 2014)
  42. Processor-Based Apparatus and Method for Processing Bit Streams (US Patent Application, December 5, 2013)
  43. Digest Generation (US Patent Application, October 31, 2013)
  44. Method and Apparatus to Process Keccak Secure Hashing Algorithm (US Patent Application, October 17, 2013)
  45. Rotate Instructions that Complete Execution without Reading Carry Flag (US Patent Application, June 30, 2011)
  46. Add Instructions to Add Three Source Operands (US Patent Application, June 23, 2011)
  47. Multiplication Instruction for Which Execution Completes without Writing a Carry Flag (US Patent Application, June 23, 2011)
  48. Method and Apparatus for Providing An Area-Efficient Large Unsigned Integer Multiplier (US Patent Application, May 5, 2011)
  49. Method and Apparatus for Performing Efficient Side-Channel Attack Resistant Reduction (US Patent Application, December 30, 2010)
  50. Unified System Architecture for Elliptic-Curve Cryptography (US Patent Application, January 1, 2009)
  51. Carry/Borrow Handling (US Patent Application, June 19, 2008)