You have to simulate the remaining logic lab experiments till 12nd of July, Sunday 23:59 and load it to LMS system. Due to time limitation, I have decreased the experiments inside each experiment mostly to 1. There are practical, visual tools available in the internet. You just place the logic components and run. As report you have to include the circuits you will design, truth table, FF table and simulation results are enough for each experiment. Simulation results must be in picture format. Otherwise it can not be opened and evaluated.