| Weekly Exp. |
Theoratical Subject |
Document Link |
| Exp.1 |
Implementation of a given circuit diagram using Logic gates |
Logic Lab Experiment #1 |
| Exp.2 |
Boolean Function Formation from Truth Table and Implementation |
Logic-Lab-Experiment-2 |
| Exp.3 |
Gate Level minimization by Karnough Map and Quine Mc Cluskey methods |
Logic-Lab-Experiment-3 |
| Exp.4 |
Multiplexers |
Logic-Lab-Experiment-4 |
| Exp.5 |
Demultiplexers, Decoders and Encoders |
Logic-Lab-Experiment-5 |
| Makeup Exp. |
Makeup lab session for students having missing or failed lab session |
Missing Lab Experiment |
| Exp.6 |
Half adder, Full adder, and subtractor logic circuits |
Experiment #6 – Modular |
| Exp.7 |
D, JK, and T type Flip-flops characteristic table verification |
Logic Lab Experiment #7 |
| Exp.8 |
Analysis of sequential Circuits |
Logic Lab Experiment #8 |
| Exp.9 |
Sequential circuit design using JK Flipflops |
Logic Lab Experiment #9 |
| Exp 10 |
Asynchronous Counters |
Logic Lab Experiment #10 |
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